PinoutSpecificationsInput Min Voltage2.7 VoltInput Max Voltage4.8 VoltOutput RangeBucks: 0.6 to 1.235V; LDO1: 0.7 to 2.2V; LDO2: 1.5 to 3.3V; LDO3 and LDO4: 0.6 to 1.25V; LDO5: 1.2 to 3.3VChannels7 ChannelsDropout Voltage0.26 VoltPowerWise TechnologyAdaptive Voltage ScalingOutput1 VoutMin0.6 VoltO...
LP5552: PinoutSpecificationsInput Min Voltage2.7 VoltInput Max Voltage4.8 VoltOutput RangeBucks: 0.6 to 1.235V; LDO1: 0.7 to 2.2V; LDO2: 1.5 to 3.3V; LDO3 and LDO4: 0.6 to 1.25V; LDO5: 1.2 to 3.3VChannels7 ...
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Input Min Voltage | 2.7 Volt |
Input Max Voltage | 4.8 Volt |
Output Range | Bucks: 0.6 to 1.235V; LDO1: 0.7 to 2.2V; LDO2: 1.5 to 3.3V; LDO3 and LDO4: 0.6 to 1.25V; LDO5: 1.2 to 3.3V |
Channels | 7 Channels |
Dropout Voltage | 0.26 Volt |
PowerWise Technology | Adaptive Voltage Scaling |
Output1 VoutMin | 0.6 Volt |
Output1 VoutMax | 1.235 Volt |
Output1 IoutMax | 800 mA |
Output1 Topology | Buck |
Output2 VoutMin | 0.6 Volt |
Output2 VoutMax | 1.235 Volt |
Output2 IoutMax | 800 mA |
Output2 Topology | Buck |
Output3 VoutMin | 1.5 |
Output3 VoutMax | 3.3 Volt |
Output3 IoutMax | 250 mA |
Output3 Topology | LDO |
Output4 VoutMin | 0.7 Volt |
Output4 VoutMax | 2.2 Volt |
Output4 IoutMax | 100 mA |
Output4 Topology | LDO |
Special Features | PowerWise 2.0 compliant with 2 slave domains. 2 Buck regulators; 5 LDOs. |
Topology | Buck, LDO |
Switching Frequency | 3600 kHz |
Adj Switch Frequency | No |
Sync Pin | No |
RegType | Power Management Unit |
Step-Down | Yes |
Step-Up | No |
Inverting | No |
Flyback | No |
Efficiency (peak) | 88 % |
Adjustable Output | Yes |
Error Flag | No |
On/Off Pin | Yes |
Multiple Output Capability | Yes |
Temperature Min | -40 deg C |
Temperature Max | +125 deg C |
PowerWise | Yes |
View Using Catalog |
The LP5552 is a PWI
The LP5552 contains 2 advanced, digitally controlled switching regulators for supplying variable voltages to a SoC or processor. The device also incorporates 5 programmable low-dropout, low-noise linear regulators for powering I/O, peripheral logic blocks, auxiliary system functions, and maintaining memory retention (dual-domains) in shutdown-mode.
The device is controlled via the high-speed serial PWI 2.0 open-standard interface. The LP5552 operates cooperatively with PowerWise
Reliability Metrics
Part Number | Process | EFR Reject | EFR Sample Size | PPM | LTA Rejects | LTA Device Hours | FITS | MTTF (Hours) |
LP5552TL | CMOS7 | 0 | 16561 | 0 | 0 | 954000 | 4 | 270700104 |
LP5552TLX | CMOS7 | 0 | 16561 | 0 | 0 | 954000 | 4 | 270700104 |
Design Tools
Title | Size in Kbytes | Date | |||
Processor Energy Savings Through Adaptive Voltage Scaling | View | ||||
Optimizing Power Consumption in the Mobile Multimedia Delivery Chain - Part One | View | ||||
Optimizing Power Consumption in the Mobile Multimedia Delivery Chain - Part Two | View |
If you have trouble printing or viewing PDF file(s), see Printing Problems. |
Application Notes
Title | Size in Kbytes | Date | |
AN-1610: Application Note 1610 LP5552 Evaluation Board | 10829 Kbytes | 20-May-08 | Download |
If you have trouble printing or viewing PDF file(s), see Printing Problems. |
More Application Notes
Title | Size in Kbytes | Date | |
AN-1653: Application Note 1653 User's Graphical User Interface(GUI) for LP555x Evaluation Board PowerWise? Technology Compliant Energy Management Unit | 1675 Kbytes | 7-Jun-07 | Download |
AN-1460: Application Note 1460 Emulating the PowerWise Interface Using GPIOs and Software | 448 Kbytes | 12-Apr-06 | Download |
AN-1857: Application Note 1857 LP5553 Evaluation Kit | 3940 Kbytes | 25-Mar-09 | Download |
AN-1467: Application Note 1467 LP5551 Evaluation Board | 32843 Kbytes | 8-Jun-07 | Download |
AN-1467 (Japanese): Application Note 1467 LP5551 Evaluation Board 640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram"> |
1847 Kbytes |
If you have trouble printing or viewing PDF file(s), see Printing Problems. |