LM2502

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V_DDA) ...................................−0.3V to +TBDV
Supply Voltage (V_DD) ....................................−0.3V to +TBDV
Supply Voltage (V_DDIO) ................................−0.3V to +TBDV
LVCMOS Input/Output Voltage .........−0.3V to (V_DDIO+0.3V)
MPL Input/Output Voltage ..............................................TBD
Junction Temperature............................................. +150°C
Storage Temperature .............................−65°C to +150°C
Lead Temperature Soldering,4 Seconds................. +260°C
ESD Ratings:HBM, 1.5 k, 100pF............................ ±2 kV
EIAJ, 0, 200 pF.................................................... ±200V
Maximum Package Power Dissipation Capacity at 25°C
TBD Package .............................................................TBD W
Derate TBD Package above 25°C ..................TBD mW/°C

The LM2502 device is a dual link Transceiver that adapts existing CPU / video busses to a low power current-mode serial MPL link.

The Master Transceiver resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Transceiver located near the display module.

Dual display support is provided for a primary and sub display through the use of two ChipSelect signals.The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted on the Master, the MD1/0 and MC signals are powered down to save current.

The LM2502 implements the physical layer of the MPL Standard (MPL-0). The MPL logic layer is currently in definition.