Features: · Fast Access Times:
15 */20/25/35/50/65/80 ns
· Full CMOS Dual Port Memory Array
· Fully Asynchronous Read and Write
· Expandable-in Width and Depth
· Full, Half-Full, and Empty Status Flags
· Read Retransmit Capability
· TTL Compatible I/O
· Packages:
28-Pin, 300-mil PDIP
28-Pin, 600-mil PDIP
32-Pin PLCC
· Pin and Functionally Compatible with IDT7201
Pinout
Specifications
| PARAMETER |
RATING |
| Supply Voltage to VSS Potential |
0.5 V to 7 V |
| Signal Pin Voltage to VSS Potential 3 |
0.5 V to VCC + 0.5 V (not to exceed 7 V) |
| DC Output Current 2 |
±50 mA |
| Storage Temperature Range |
65 to 150 |
| Power Dissipation (Package Limit) |
1.0 W |
| DC Voltage Applied To Outputs In High-Z State |
0.5 V to Vcc + 0.5 V (not to exceed 7 V) |
NOTES:
1. Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above those indicated in the 'Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
3. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.
DescriptionThe LH5496/96H are dual port memories with internal addressing to implement a First-In, First-Out algorithm.
Through an advanced dual port architecture, they provide fully asynchronous read/write operation. Empty, Full, and
Half-Full status flags are provided to prevent data overflow and underflow. In addition, internal logic provides for
unlimited expansion in both word size and depth.
Read and write operations automatically access sequential locations in memory in that data is read out in the
same order that it was written, that is on a First-In, First-Out basis. Since the address sequence is internally
predefined, no external address information is required for the operation of this device. A ninth data bit is provided
for parity or control information often needed in communication applications.
Empty, Full, and Half-Full status flags monitor the extent to which data has been written into the LH5496, and prevent improper operations (i.e., Read if the FIFO is empty, or Write if the FIFO is full). A retransmit feature resets the Read address pointer to its initial position, thereby allowing repetitive readout of the same data. Expansion In and Expansion Out pins implement an expansion scheme that allows individual FIFOs to be cascaded to greater depth without incurring additional latency (bubblethrough) delays.
LH5496 Data Sheet
