LCPDL-TTL-7-1

The LCPDL-TTL-7-1 is designed as low profile T2L compatible 3-bit leadless chip carrier programmable logic delay line. It is offered in 22 modules with time delays to a maximum of 357ns and with step resolution.

The LCPDL-TTL-7-1 has eight features. The first one is it would have T2L input and output. The next one is pulse stable and precise. The next one is leadless chip carrier (0.240 high). The next one is available in delays up to 357ns. The next one is it would be available in 22 delay steps with resolution from 1ns to 50ns. The next one is propagation delays fully compensated. The next one is all pulse widths digitally programmable. The next one is 10 T2L fan-out capacity. That are all the main features.

Some important operating specifications of LCPDL-TTL-7-1 have been concluded into several points as follow. The first one is about its Vcc supply voltage which would be from 4.75 to 5.25Vdc. The next one is about its Vcc supply current which would be 40mA typical. The next one is about its logic 1 input voltage which would be 2V min and 5.5V max. The next one is about its logic 1 input current (-1 to -5) which would be 3.5V = 4mA max and -6 through -10 it would be 3.5V = 17mA max and -11 through -50 it would be 3.5V = 20mA max. The next one is about its logic 0 input voltage which would be 0.8V max. The next one is about its logic 0 input current which would be 0.25V = -5mA max. The next one is about its logic 1 voltage out which would be min 2.4V. The next one is about its logic 0 voltage out which would be 0.5V max. The next one is about its operating temperature range which would be 0 to 70°C. The next one is about its storage temperature range which would be from -55 to +125°C. It should be noted that delays increase or decrease approximately 2% for a respective increase or decrease of 5% in supply voltage. And so on. For more information please contact us.