LC876696A

(1) Read-Only Memory (ROM): LC8766C8A 131072 * 8 bits
                                                LC8766B2A 114688 * 8 bits
                                                LC876696A 98304 * 8 bits
(2) Random Access Memory (RAM): LC8766C8A/B2A/96A         4096 * 9 bits
(3) Minimum Bus Cycle Time: 100ns (10MHz)
      Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300ns (10MHz)
(5) Ports
     - Input/output ports
       Data direction programmable for each bit individually :     20 (P1n, P70 to P73, P8n)
     - 15V withstand input/output ports
       Data direction programmable in nibble units :                   8 (P0n)
       (When N-channel open drain output is selected, data can be input in bit units.)
       Data direction programmable for each bit individually :     8 (P3n)
     - Input ports : 2 (XT1,XT2)
     - VFD output ports
       Large current outputs for digits :                                      9 (S0 / T0 to S8 / T8)
       Large current outputs for digits / segments :                   7 (S9 / T9 to S15 / T15)
       digit / segment outputs :                                                  8 (S16 to S23)
       segment outputs :                                                            28 (S24 to S51)
       Other functions
       Input/output ports :                                                         12(PFn, PG0 to 3)
       Input ports :                                                                     24 (PCn, PDn, PEn)
    - Oscillator pins :                                                                  2 (CF1,CF2)
    - Reset pin :                                                                         1 (RES#)
    - Power supply :                                                                  6 (VSS1 to 2, VDD1 to4)
    - VFD power supply :                                                           1 (VP)
(6) VFD automatic display controller
    - Programmable segment/digit output pattern
      Output can be switched between digit/segment waveform output (pins 9 to 24 can be used for output of digit waveforms).
      parallel-drive available for large current VFD.
   - 16-step dimmer function available
(7) Weak signal detection (MIC signals etc)
   - Counts pulses with width greater than a preset value
   - 2 bit counter
(8) Timers
   - Timer 0: 16 bit timer / counter with capture register
      Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
      Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
                    Counter with 8-bit capture register
      Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
      Mode 3: 16 bit counter with 16 bit capture register
    - Timer 1: PWM / 16 bit timer toggle output
      Mode 0: 2 channel 8 bit timer (with toggle output)
      Mode 1: 2 channel 8 bit PWM
      Mode 2: 16 bit timer (with toggle output) Toggle output also possible using lower order 8 bits.
      Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.
    - Base Timer
   1) The clock signal can be selected from any of the following :
       Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
   2) Interrupts can be selected to occur at one of five different times.
(9) High speed clock counter
    1) Capable of counting maximum: 20MHz clock (Using main clock 10MHz)
    2) Real time output
(10) Serial-interface
     - SIO 0: 8 bit synchronous serial Interface
    1) LSB first / MSB first function available
    2) Internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 Tcyc)
    3) Continuous automatic data communication (1-256 bits)
    - SIO 1: 8 bit asynchronous / synchronous serial interface
       Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2512 Tcyc)
       Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 82048Tcyc)
       Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2512 Tcyc)
       Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
       -8 bits * 12 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
       -Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc)
(13) Watchdog timer
      - The watching timer period is set using an external RC.
      - Watchdog timer can produce interrupt, system reset
(14) Interrupts: 15-source, 10-vectored interrupts
     1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is refused.
     2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
        In the case of equal priority levels, the vector with the lowest address takes precedence.
(15) Subroutine stack levels: 2048 levels max. Stack is located in RAM.
(16) Multiplication and division
       - 16 bit * 8 bit (executed in 5 cycles)
       - 24 bit * 16 bit (12 cycles)
       - 16 bit ÷ 8 bit (8 cycles)
       - 24 bit ÷ 16 bit (12 cycles)
(17) Oscillation circuits
      - On-chip RC oscillation circuit for system clock use.
      - On-chip CF oscillation circuit for system clock use. (Rf built in)
      - On-chip Crystal oscillation circuit low speed system clock use. (Rd, Rf external)
(18) System clock divider function
      - Able to reduce current consumption
       Available minimum instruction cycle time: 300ns, 600ns, 1.2µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs.
       (Using 10MHz main clock)
(19) Standby function
     - HALT mode
       HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits stilloperate but VFD display and some serial transfer operations stop.
    1) Oscillation circuits are not stopped automatically.
    2) Release occurs on system reset or by interrupt.
    -HOLD mode
     HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits arestopped.
    1)CF, RCand crystal oscillation circuits stop automatically.
    2) Release occurs on any of the following conditions.
   (1) input to the reset pin goes low
   (2) a specified level is input at least one of INT0, INT1, INT2
   (3) an interrupt condition arises at port 0
   -X'tal HOLD made
    X'tal HOLD mode is used to reduce power consumption. Program execution is stopped.
    All peripheral circuits except the base timer are stopped.
    1) CF and RC oscillation circuits stop automatically.
    2) Crystal oscillator is maintained in its state at HOLD mode inception.
    3) Release occurs on any an any of the following conditions
   (1) input to the reset pin goes low
   (2) a specified level is input to at least one of INT0, INT1, INT2
   (3) an interrupt condition arises at port 0
   (4) an interrupt condition arises at the base-timer
(20) Factory shipment
    -delivery form QIP100E
(21) Development tools
   - Evaluation chip: LC876095
   - Emulator: EVA62S + ECB876600 (Evaluation chip board) + SUB876500 + POD100QFP
   - Flash ROM version: LC87F66C8A