LC876572A

(1) Read-Only Memory (ROM): LC876572A 73728 × 8 bits
                                                LC876564A 65536 × 8 bits
(2) Random Access Memory (RAM): LC876572A/64A 2048 × 9 bits
(3) Minimum Bus Cycle Time: 100 ns (10 MHz)
      Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300 ns (10MHz)
(5) VFD automatic display controller
     - Programmable segment/digit output pattern
     Output can be switched between digit/segment waveform output (pins 9?u24 can be used for output of digit  waveforms.
      parallel-drive available for large current VFD.
     - 16-step dimmer function available
(6) Weak signal detection (MIC signals etc)
     - Counts pulses with width greater than a preset value
     - 2 bit counter
(7) AD converter
     -8 bits × 12 channels
(8) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
     -Noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 Tcyc)
(9) Watchdog timer
    - The watching timer period is set using an external RC.
    - Watchdog timer can produce interrupt, system reset
(10) Interrupts: 15-source, 10-vectored interrupts
   1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is refused.
  2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.In the case of equal priority levels, the vector with the lowest address takes precedence.
(11) Subroutine stack levels: 1024 levels max. Stack is located in RAM.