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LC24000

Features: • Support for 2-million gate devices using a SANYO-developed 0.35-m 3-metal layer technology.• These 0.35-m ASICs can interface with either 3.3-V or 5-V external signals without the use of any special external circuits even in a system where both 3.3-V and 5-V circuits are co...

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SeekIC No. : 004391565 Detail

LC24000: Features: • Support for 2-million gate devices using a SANYO-developed 0.35-m 3-metal layer technology.• These 0.35-m ASICs can interface with either 3.3-V or 5-V external signals withou...

LC24000 Data Sheet

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Part Number:
LC24000
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Support for 2-million gate devices using a SANYO-developed 0.35-m 3-metal layer technology.
• These 0.35-m ASICs can interface with either 3.3-V or 5-V external signals without the use of any special external circuits even in a system where both 3.3-V and 5-V circuits are combined on the same board .
• An extensive lineup of megacells supports the development of large-scale system ICs.
• Our customers custom circuits and ASSPs designed using ASIC techniques can be integrated on a single chip.
• Power dissipation can be estimated precisely at simulation time using power simulator "A Power". Power dissipation is estimated precisely by referencing a library of current drain values that depend on the load capacitance and individual cell waveform distortions based on the Verilog*2 simulation file.
• The adoption of Quick Port, which is an inter-ASIC transplant tool that adopts the HDA concept, allows data migration between ASPEC libraries to be performed easily in the layout database. While it goes without saying that data migration can be performed easily in the layout database for data from the same vendor, this system also supports data migration between data from different vendors.
• FPGA designs can be easily converted to these ASIC products.
• Full scan is supported for test design.
• A high-level language (RTL) interface is supported.


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