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KT8557B

Features: ·Complete CODEC and filtering system ·Meets or exceeds AT&T D3/D4 and CCITT specifications m-Law : KT8554B, A-Law : KT8557B ·On-chip auto zero, sample and hold, and precision voltage references ·Low power dissipation : 60mW (operating) 3mW (standby)·± 5V operation ·TTL or CMOS compat...

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KT8557B: Features: ·Complete CODEC and filtering system ·Meets or exceeds AT&T D3/D4 and CCITT specifications m-Law : KT8554B, A-Law : KT8557B ·On-chip auto zero, sample and hold, and precision voltage r...

KT8557B Data Sheet

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Part Number:
KT8557B
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·Complete CODEC and filtering system
·Meets or exceeds AT&T D3/D4 and CCITT specifications m-Law : KT8554B, A-Law : KT8557B
·On-chip auto zero, sample and hold, and precision voltage references
·Low power dissipation : 60mW (operating)  3mW (standby) 
·± 5V operation
·TTL or CMOS compatible
·Automatic power down


Specifications

Characteristic Symbol Value Unit
Positive Supply Voltage
Negative Supply Voltage
Voltage at Any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secs)		 VCC
VBB
VI(A)
Vl(D)
Ta
TSTG
TLEAD		 7
- 7
VCC + 0.3 to VBB -0.3
VCC+ 0.3 to GNDA- 0.3
- 25 to + 125
- 65 to + 150
300		 V
V
V
V





Description

Pin No Symbol Description
1 VBB
VBB = -5V±5%.

2 GNDA Analog ground.
3 VFRO
 Analog output of the receive power Amp.
4 VCC VCC = +5V±5%
5 FSR Receive frame sync pulse. 8KHz pulse train.
6 DR PCM data input.
7 BCLKR
/CLKSEL		 Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master
clock in normal operation and BCLKX is used for both TX and RX directions.
Alternately direct clock input available, very from 64KHz to 2.048MHz.
8 MCLK /R
PDN		 When MCLKR is connected continuously high, the device is powered down.
Normally connected continusously low, MCLKX is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
9 MCLKX Must be1.536MHz/1.544MHz or 2.048MHz.
10 BCLKX May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLKX
in normal operation.
11 DX PCM data output.
12 FSX TX frame sync pulse. 8KHz pulse train.
13 TSX Changed from high to low during the encoder timeslot. Open drain output.
14 GSX Analog output of the TX input amplifier.
Used to set gain through external resistor.
15
VFXI-
 Inverting input stage of the TX analog signal.
16
VFXI+
 Non-inverting input stage of the TX analog signal.Non-inverting input stage of the TX analog signal.



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