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KM416S1021C

Features: • JEDEC standard 3.3V power supply• SSTL_3 (Class II) compatible with multiplexed address• Dual banks operation• MRS cycle with address key programs- CAS latency (2 & 3)- Burst length (1, 2, 4, 8 & Full page)- Burst type (Sequential & Interleave)•...

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SeekIC No. : 004386050 Detail

KM416S1021C: Features: • JEDEC standard 3.3V power supply• SSTL_3 (Class II) compatible with multiplexed address• Dual banks operation• MRS cycle with address key programs- CAS latency (2...

KM416S1021C Data Sheet

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Part Number:
KM416S1021C
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• JEDEC standard 3.3V power supply
• SSTL_3 (Class II) compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)


Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1.0 W
Short circuit current IOS 50 mA

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The KM416S1021C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG¢s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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