KK74AC373

Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	-0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
VOUT	DC Output Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
IIN	DC Input Current, per Pin	±20	mA
IOUT	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC Supply Current, VCC and GND Pins	±50	mA
PD	Power Dissipation in Still Air, Plastic DIP+                                        SOIC Package+	750 500	mW
TSTG	Storage Temperature	-65 to +150
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)	260

*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
  +Derating - Plastic DIP: - 10 mW/ from 65° to 125
  SOIC Package: : - 7 mW/ from 65° to 125



Description

The KK74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may enabled.