KK74AC193

Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA




Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	-0.5 to +7.0	V
VIN	DC Input Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
VOUT	DC Output Voltage (Referenced to GND)	-0.5 to VCC +0.5	V
IIN	DC Input Current, per Pin	±20	mA
IOUT	DC Output Sink/Source Current, per Pin	±50	mA
ICC	DC Supply Current, VCC and GND Pins	±50	mA
PD	Power Dissipation in Still Air, Plastic DIP+                                         SOIC Package+	750 500	mW
TSTG	Storage Temperature	-65 to +150
TL	Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)	260

*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
  +Derating - Plastic DIP: - 10 mW/ from 65° to 125
             SOIC Package: : - 7 mW/ from 65° to 125





Description

The KK74AC193 is identical in pinout to the LS/ALS193, HC/HCT193. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TC_D) and Terminal Count Up (TC_U) Outputs are provided to enable cascading of both up and down counting functions. The TC_D output produces a negative going pulse when the counter underflows and TC_U outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TC_U and TC_D outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device.