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KK74AC175

Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A; 0.1 A @ 25°C• High Noise Immunity Characteristic of CMOS Devices• Outputs Source/Sink 24 mAPinoutSpecifications SYMBOL CHARACTERISTICS...

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SeekIC No. : 004385709 Detail

KK74AC175: Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A; 0.1 A @ 25°C• High Noise Immunity Characterist...

KK74AC175 Data Sheet

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Part Number:
KK74AC175
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A; 0.1 A @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA


Pinout

Connection Diagram


Specifications

SYMBOL CHARACTERISTICS MAX UNIT
VCC

VIN		 Supply Voltage(Referenced to GND)

DC Input Voltage (Referenced to GND)		 -0.5 to +7.0

-0.5 to VCC +0.5		 V

V
VOUT DC Output Voltage(Referenced to GND) -0.5 to VCC +0.5 V
IIN

DC Input Current, per Pin

 ±20 mA
IOUT DC Output Sink/Source Current, per Pin ±50 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD
 Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750
500		 mW
Tstg Storage Temperature -65 to 150
TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260


*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65° to 125
SOIC Package: : - 7 mW/ from 65° to 125




Description

The KK74AC175 is identical in pinout to the LS/ALS175, HC/HCT175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs.

This device consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the Clock input.




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