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KK74AC138

Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A; 0.1 A @ 25°C• High Noise Immunity Characteristic of CMOS Devices• Outputs Source/Sink 24 mAPinoutSpecifications Symbol Parameter ...

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SeekIC No. : 004385698 Detail

KK74AC138: Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A; 0.1 A @ 25°C• High Noise Immunity Characterist...

KK74AC138 Data Sheet

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Part Number:
KK74AC138
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A; 0.1 A @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA


Pinout

Connection Diagram


Specifications

Symbol
 Parameter
Value
Unit
VCC
 DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
 Power Dissipation in Still Air, Plastic DIP, SOIC Package
750
500
mW
Tstg
 Storage Temperature
-65 to +150
TL
 Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65to 125
SOIC Package: : - 7 mW/ from 65° to 125


Description

The KK74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The KK74AC138 decodes a three-bit Address to one-of-eight active-low outputs. This device features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states.

 




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