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KK4043B

Features: `Operating Voltage Range: 3.0 to 18 V `Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 `Noise margin (over full package temperature range): 1.0 V min@5.0 V supply 2.0 V min@10.0 V supply 2.5 V min @ 15.0 V supply PinoutSpecifications ...

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SeekIC No. : 004385619 Detail

KK4043B: Features: `Operating Voltage Range: 3.0 to 18 V `Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25 `Noise margin (over full package temperature range): ...

KK4043B Data Sheet

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Part Number:
KK4043B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Description



Features:

`Operating Voltage Range: 3.0 to 18 V  
`Maximum input current of 1 A at 18 V over full package-temperature
   range; 100 nA at 18 V and 25  
`Noise margin (over full package temperature range):
                                                 1.0 V min@5.0 V supply 
                                                 2.0 V min@10.0 V supply
                                                 2.5 V min @ 15.0 V supply


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5
V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5
V
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+ 
                                        SOIC Package+ 		750
500 		mW
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 		260



Description

The  KK4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and dividual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1"or high on the ENABLE input connects the latch states to the Q outputs. A logic "0"or low on the ENABLE input disconnects the latch tates   outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.




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