KK4021B

The KK4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-Serial Converter) with a synchronous Serial Data Input (DS), a Clock Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight asynchronous Parallel Data Inputs (P0-P7) and Buffered Parallel Outputs from the last three stages (Q5-Q7).

Information on the Parallel Data Inputs (P0-P7) is asynchronously loaded into the register while the Parallel Load Input (PL) is HIGH, independent of the Clock (CP) and Serial Data (DS) inputs. Data present in the register is stored on the HIGH-to-LOW transition of the Parallel Load Input (PL).

When the Parallel Load Input is LOW, data on the Serial Data Input (DS) is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of the Clock Input (CP).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply