Position: Home  > All Categories> Integrated Circuits (ICs) > K7R323682M

K7R323682M

Features: • 1.8V+0.1V/-0.1V Power Supply.• DLL circuitry for wide output data valid window and future freguency scaling.• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,1.8V+0.1V/-0.1V for 1.8V I/O.• Separate independent read and write data ports with concurrent read and w...

product image

K7R323682M Picture
See larger image
SeekIC No. : 004383340 Detail

K7R323682M: Features: • 1.8V+0.1V/-0.1V Power Supply.• DLL circuitry for wide output data valid window and future freguency scaling.• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,1.8V+0.1V/...

K7R323682M Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
K7R323682M
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/24

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,1.8V+0.1V/-0.1V for 1.8V I/O.
• Separate independent read and write data ports with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock rising edges only.
• Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data traceability.
• Single address bus.
• Byte write (x9, x18, x36) function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm



Specifications

PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.5 to 2.9 V
Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V
Voltage on Input Pin Relative to VSS VIN -0.5 to VDD+0.3 V
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TOPR 0 to 70 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.




Description

The K7R323682M,K7R321882M and K7R320982M are 37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.They are organized as 524,288 words by 36bits for K7Q163682A and 1,048,576 words by 18 bits for K7Q161882A.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,the data outputs are synchronized to the input clocks ( K and K ).Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks.Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.Synchronous pipeline read and early write enable high speed operations.Simple depth expansion is accomplished by using R and W for port selection.Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins.IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7R323682M,K7R321882M and K7R320982M are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Industrial Controls, Meters
SGDM-15ADA
41AA1600E
Hardware, Fasteners, Accessories
MF-A02
LMS700KF07
Relays
WIMA MKP4 0.22UF 630V
WIMA MKP4 4.7UF 630VDC
Optoelectronics
SFH7770
TLP423J
Connectors, Interconnects
ASP-134488-01
WM4078-ND
Inductors, Coils, Chokes
DR127-330-R
SD53-100-R
View more