K7Q161854A

*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V_DDQ must not exceed VDD during normal operation.

The K7Q163654A and K7Q161854A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.They are organized as 524,288 words by 36bits for K7Q163682A and 1,048,576 words by 18 bits for K7Q161882A.

The QDR K7Q161854A operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,the data outputs are synchronized to the input clocks ( K and K ).Read address is registered on rising edges of the input K clocks, and write address is registered on rising edges of the input K clocks.Common address bus is used to access address both for read and write operations.

The internal burst counter K7Q161854A is fiexd to 2-bit sequential for both read and write operations.Synchronous pipeline read and early write enable high speed operations.Simple depth expansion is accomplished by using R and W for port selection.Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins.IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7Q163654A and K7Q161854A are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.