K7M161825A

Features:

• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.


Pinout




Specifications

PARAMETER		SYMBOL	RATING	UNIT
Voltage on VDD Supply Relative to VSS		VDD	-0.3 to 4.6	V
Voltage on Any Other Pin Relative to VSS		VIN	-0.3 to VDD+0.3	V
Power Dissipation		PD	1.6	W
Storage Temperature		TSTG	-65 to 150	°C
Operating Temperature	Commercial	TOPR	0 to 70	°C
	Industrial	TOPR	-40 to 85	°C
Storage Temperature Range Under Bias		TBIAS	-10 to 85	°C

Description

The K7M163625A and K7M161825A are 18,874,368-bits Synchronous Static SRAMs.
The NtRAM^TM, or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the risin edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array.
The K7M163625A and K7M161825A are implemented with SAMSUNG¢s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce.