K7B801825M

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The K7B803625M and K7B801825M are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. 

The K7B801825M is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications;GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high.And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC)inputs. Subsequent burst addresses are generated internally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input.

LBOpin is DC operated and determines burst sequence(linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.

The K7B801825M is fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.