Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• On-Chip Address Counter.• Self-Timed Write Cycle.• On-Chip Address and Control Registers.• 3.3V+0.165V/-0.165V Power Supply.• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O...
K7A801809A: Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• On-Chip Address Counter.• Self-Timed Write Cycle.• On-Chip Address and Control Registers....
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Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• O...
Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• O...
Features: • Synchronous Operation.• 2 Stage Pipelined operation with 4 Burst.• O...
PARAMETER | SYMBOL |
RATING |
UNIT |
Voltage on VDD Supply Relative to VSS | VDD |
0.3 to 4.6 |
V |
Voltage on VDDQ Supply Relative to VSS | VDDQ |
VDD |
V |
Voltage on Input Pin Relative to VSS | VIN |
0.3 to 4.6 |
V |
Voltage on I/O Pin Relative to VSS | VIO |
-0.3 to VDDQ+0.5 |
V |
Power Dissipation | PD |
1.6 |
W |
Storage Temperature | TSTG |
-65 to 150 |
|
Operating Temperature | TOPR |
0 to 70 |
|
Storage Temperature Range Under Bias | TBIAS |
10 to 85 |
The K7A803609A and K7A801809A are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.
The K7A801809A is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.
The K7A803609A and K7A801809A are fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP and 119BGA package. Multiple power and ground pins are utilized to minimize ground bounce.