K5P2880YCM-T085

NOTE :
1.
Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCCQ+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The K5P2880YCM-T085 featuring single 3.0V power supply is a Multi ChipPackage Memory which combines 128Mbit Nand Flash and 8Mbit full CMOS SRAM.

The 128Mbit Flash memory K5P2880YCM-T085 is organized as 16M x8 bit and the 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. In 128Mb NAND Flash a 528-byte page program can be typically achieved within 300us and an 16K-byte block erase can be typically achieved within 2ms. In serial read operation, a byte can be read by 50ns. The I/O pins serve as the ports for address and data input/output as well as command inputs. Even the write-intensive systems can take advantage of the FLASH¢s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 8Mbit SRAM supports the low data retention voltage for battery backup operation with low current.

The K5P2880YCM-T085 is suitable for use in data memory of mobil communication system to reduce not only mount area but also power consumption. This K5P2880YCM-T085 is available in 69-ball TBGA Type.