K5L5628JT(B)M

<Common>
• Operating Temperature : -30°C ~ 85°C
• Package : 115Ball FBGA Type - 8.0mm x 12.0mm
0.8mm ball pitch
1.4mm (Max.) Thickness
<NOR Flash>
• Single Voltage, 1.7V to 1.95V for Read and Write operations
• Organization
- 16,772,216 x 16 bit ( Word Mode Only)
• Read While Program/Erase Operation
• Multiple Bank Architecture
- 16 Banks (16Mb Partition)
• OTP Block : Extra 256Byte block
• Read Access Time (@ CL=30pF)
- Asynchronous Random Access Time :
90ns (54MHz) / 80ns (66MHz)
- Synchronous Random Access Time :
88.5ns (54MHz) / 70ns (66MHz)
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz)
• Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
• Block Architecture
- Eight 4Kword blocks and five hundreds eleven 32Kword blocks
- Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword blocks
- Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks
• Reduce program time using the VPP
• Support Single & Quad word accelerate program
• Power Consumption (Typical value, CL=30pF)
- Burst Access Current : 30mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 25uA
• Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V_IL
- All blocks are protected by V_PP=V_IL
• Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Program/Erase
• Hardware Reset (RESET)
• Data Polling and Toggle Bits
- Provides a software method of detecting the status of program or erase completion
• Endurance 100K Program/Erase Cycles Minimum
• Data Retention : 10 years
• Support Common Flash Memory Interface
• Low Vcc Write Inhibit
<UtRAM>
• Process Technology: CMOS
• Organization: 8M x16 bit
• Power Supply Voltage: V_CC 2.5~2.7V, V_CCQ 1.7~2.0V
• Three State Outputs
• Supports MRS (Mode Register Set)
• MRS control - MRS Pin Control
• Supports Power Saving modes - Partial Array Refresh modeInternal TCSR
• Supports Driver Strength Optimization for system environment power saving.
• Supports Asynchronous 4-Page Read and Asynchronous WriteOperation
• Supports Synchronous Burst Read and Synchronous Burst Write Operation
• Synchronous Burst(Read/Write) Operation
- Supports 4 word / 8 word / 16 word and Full Page(256 word) burst
- Supports Linear Burst type & Interleave Burst type
- Latency support : Latency 3 @ 52.9MHz(tCD 12ns)
- Supports Burst Read Suspend in No Clock toggling
- Supports Burst Write Data Masking by /UB & /LB pin control
- Supports WAIT pin function for indicating data availability.
• Max. Burst Clock Frequency : 52.9MHz

Notes :
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -1.5V for periods <20ns.
Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+1.5V for periods <20ns.
2. Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -1.5V for periods <20ns.
Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +11.0V for periods <20ns.
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The K5L5628JT(B)M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and 128Mbit Synchronous Burst UtRAM.256Mbit Synchronous Burst Multi Bank NOR Flash Memory K5L5628JT(B)M is organized as 16M x16 bits and 128Mbit Synchronous Burst UtRAM is organized as 8M x16 bits.

In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device K5L5628JT(B)M is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture K5L5628JT(B)M provides highly flexible erase and program capability.

The NOR Flash consists of sixteen banks. This device K5L5628JT(B)M  is capable of reading data from one bank while programming or erasing in the other bank.

Regarding read access time, the K5L5628JT(B)M  provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz, the device provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of 16 bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current.

In 128Mbit Synchronous Burst UtRAM, the K5L5628JT(B)M  is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These two bus operation modes are defined through the mode register setting. The device also supports the special features for the standby power saving.

Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode.
The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings.

Through this driver strength optimization, the K5L5628JT(B)M  can minimize the noise generated on the data bus during read operation.

The K5L5628JT(B)M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 115-ball FBGA Type.