K4T56043QF-GCD5

Note :
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

The 256Mb DDR2 SDRAM chip K4T56043QF-GCD5 is organized as either 16Mbit x 4 I/Os x 4 banks or 8Mbit x 8 I/Os x 4banks device. This synchronous device K4T56043QF-GCD5 achieves high speed double-data-rate transfer rates of up to 667Mb/sec/pin (DDR2-667) for general applications.

The chip K4T56043QF-GCD5 is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive atency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row,column,and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x4) device receive 13/11/2 addressing.

The 256Mb DDR2 device K4T56043QF-GCD5 operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.

The 256Mb DDR2 device K4T56043QF-GCD5 is available in 60ball FBGAs(x4/x8).