Features: • 1.8V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs.-. CAS latency (1, 2 & 3).-. Burst length (1, 2, 4, 8 & Full page).-. Burst type (Sequential & Interleave).• EMRS cycle ...
K4M28163PF-R(B)G/F: Features: • 1.8V power supply.• LVCMOS compatible with multiplexed address.• Four banks operation.• MRS cycle with address key programs.-. CAS latency (1, 2 & 3).-. Burst...
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• 1.8V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls FBGA with 0.8mm ball pitch ( -RXXX : Leaded, -BXXX : Lead Free).
Parameter | Symbol | Value | Unit |
Voltage on any pin relative to Vss | VIN, VOUT | -1.0 ~ 4.6 | V |
Voltage on VDD supply relative to Vss | VDD ,VDDQ | -1.0 ~ 4.6 | V |
Storage temperature | TSTG | -55 ~ +150 | °C |
Power dissipation | PD | 1.0 | W |
Short circuit current | IOS | 50 | mA |
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The K4M28163PF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits,fabricated with SAMSUNG's high performance CMOS technology.Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.