K4H561638H-UCCC

DescriptionThe K4H561638H-UCCC is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 / 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up...

product image

K4H561638H-UCCC Picture
SeekIC No. : 004382818 Detail

K4H561638H-UCCC: DescriptionThe K4H561638H-UCCC is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 / 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNGs high pe...

floor Price/Ceiling Price

Part Number:
K4H561638H-UCCC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/24

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Description

The K4H561638H-UCCC is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x 8,388,608 / 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

The feature of the K4H561638H-UCCC are:(1)VDD : 2.5V ± 0.2V, VDDQ :  2.5V ± 0.2V for DDR266, 333 ; (2)VDD : 2.6V ± 0.1V, VDDQ :  2.6V ± 0.1V for DDR400; (3)Double-data-rate architecture; two data transfers per clock cycle; (4)Bidirectional data strobe [DQS] (x4,x8)  &  [L(U)DQS] (x16) ; (5)Four banks operation; (6)Differential clock inputs(CK and CK); (7)DLL aligns  DQ and DQS transition with CK transition; (8)MRS cycle with address key programs-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)-. Burst length (2, 4, 8)-. Burst type (sequential & interleave); (9)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (10)Data I/O transactions on both edges of data strobe ; (11)Edge aligned data output, center aligned data input; (12)LDM,UDM for write masking only (x16); (13)DM for write masking only (x4, x8); (14)Auto & Self refresh; (15)7.8us refresh interval(8K/64ms refresh) ; (16)Maximum burst refresh cycle : 8; (17)66pin TSOP II Pb-Free package.

The absolute maximum ratings of the K4H561638H-UCCC can be summarized as:(1)Voltage on any pin relative to VSS VIN, VOUT:-0.5 ~ 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ :-1.0 ~ 3.6 V; (3)Storage temperature TSTG :-55 ~ +150 °C; (4)Power dissipation PD: 1.5 W; (5)Short circuit current IOS :50 mA .   

If you want to know more information such as the electrical AC characteristics ,please download the datasheet in www.seekdatasheet.com .




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Static Control, ESD, Clean Room Products
RF and RFID
Resistors
LED Products
View more