Position: Home  > All Categories> Integrated Circuits (ICs) > K4H561638F

K4H561638F

Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe L(U)DQS• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs...

product image

K4H561638F Picture
See larger image
SeekIC No. : 004382810 Detail

K4H561638F: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe L(U)DQS• Four banks operation• Differential clock inputs(CK and CK)&#...

K4H561638F Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
K4H561638F
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe L(U)DQS
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
   -. Read latency 2, 2.5 (clock)
   -. Burst length (2, 4, 8)
   -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1.5 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if Absolute Maximum Rating are exceeded.
           Functional operation should be restricted to recommend operation condition.
           Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The K4H560838F / K4H561638F is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 4/16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Resistors
A101G
3006P-1-205LF
Undefined Category
VI-B63-IU
X27 589
Industrial Controls, Meters
SGDM-15ADA
41AA1600E
Audio Products
HUC1002
WM-64CT
Memory Cards, Modules
WT32
VTL5C7
Computers, Office - Components, Accessories
DS-4008HCI
LB104V03(A1)
View more