Position: Home  > All Categories> Integrated Circuits (ICs) > K4H560838F-UCC4

K4H560838F-UCC4

Features: • 200MHz Clock, 400Mbps data rate.• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V• Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns...

product image

K4H560838F-UCC4 Picture
See larger image
SeekIC No. : 004382808 Detail

K4H560838F-UCC4: Features: • 200MHz Clock, 400Mbps data rate.• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V• Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data s...

K4H560838F-UCC4 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
K4H560838F-UCC4
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/30

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant


Pinout

Connection Diagram


Specifications

Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD,VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.5
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Test Equipment
TOP853
TOP2005
Boxes, Enclosures, Racks
ACLSN12
ACLJIC
Batteries, Chargers, Holders
ICR18650-28A
ICR18650-26F/h
Capacitors
GRM188R71H103KA01D
GRM21BR71H104KA01L
Power Supplies - Board Mount
HC-06
PM150RSA060-S81AH0G
Programmers, Development Systems
ARDUINO IIC/I2C 液晶模块
JTAG-SMT2
View more