K4H560838E-UCB0

The K4H560838E-UCB0 is designed as DDR SDRAM 256Mb E-die (x8) which would be Pb-free.

The K4H560838E-UCB0 has many features. (1) Double-data-rate architecture; two data transfers per clock cycle. (2) Bidirectional data strobe (DQS). (3) Four banks operation. (4) Differential clock inputs(CK and CK). (5) DLL aligns DQ and DQS transition with CK transition. (6) MRS cycle with address key programs which means read latency 2, 2.5 (clock), burst length (2, 4, 8) and burst type (sequential & interleave). (7) All inputs except data & DM are sampled at the positive going edge of the system clock(CK). (8) Data I/O transactions on both edges of data strobe. (9) Edge aligned data output, center aligned data input. (10) DM for write masking only (x4, x8). (11) Auto & self refresh. (12) 7.8us refresh interval(8K/64ms refresh). (13) Maximum burst refresh cycle : 8. (14) 66pin TSOP II Pb-free package. (15) RoHS compliant. That are all the main features.

Some absolute maximum ratings of K4H560838E-UCB0 have been concluded into several points as follow. (1) Its voltage on any pin relative to Vss would be from -0.5V to 3.6V. (2) Its voltage on Vdd supply relative to Vss would be from -1.0V to 3.6V. (3) Its storage temperature would be from -55°C to +150°C. (4) Its power dissipation would be 1.5W. (5) Its short circuit current would be 50mA. It should be noted that permanent device damage may occur if "absolute maximum ratings" are exceeded.

Also some DC operating conditions about K4H560838E-UCB0. (1) Its supply voltage should be min 2.3V and max 2.7V. (2) Its input logic high voltage should be min Vref+0.15V and max Vddq+0.3V. (3) Its input logic low voltage should be min -0.3V and max Vref-0.15V. (4) Its input leakage current would be min -2uA and max 2uA. (5) Its I/O supply voltage would be min 2.3V and max 2.7V. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!