Features: * Double-data-rate architecture; two data transfers per clock cycle* Bidirectional data strobe(DQS)* Four banks operation* Differential clock inputs(CK and CK)* DLL aligns DQ and DQS transition with CK transition* MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Bu...
K4H560438D-NC: Features: * Double-data-rate architecture; two data transfers per clock cycle* Bidirectional data strobe(DQS)* Four banks operation* Differential clock inputs(CK and CK)* DLL aligns DQ and DQS trans...
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Features: • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333 • VDD : 2.6V ± 0.1V, VDDQ...
Features: • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333 • VDD : 2.6V ± 0.1V, VDDQ...
Features: • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333 • VDD : 2.6V ± 0.1V, VDDQ...
Parameter |
Symbol |
Value |
Unit |
Voltage on any pin relative to VSS |
VIN, VOUT |
-0.5 ~ 3.6 |
V |
Voltage on VDD & VDDQ supply relative to VSS |
VDD, VDDQ |
-1.0 ~ 3.6 |
V |
Storage temperature |
TSTG |
-55~ +150 |
|
Power dissipation |
PD |
1.5 |
W |
Short circuit current |
IOS |
50 |
mA |