Position: Home  > All Categories> Integrated Circuits (ICs) > K4H56038D

K4H56038D

Features: • 200MHz Clock, 400Mbps data rate.• VDD= +2.6V +0.10V, VDDQ= +2.6V +0.10V • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK )• DLL aligns...

product image

K4H56038D Picture
See larger image
SeekIC No. : 004382787 Detail

K4H56038D: Features: • 200MHz Clock, 400Mbps data rate.• VDD= +2.6V +0.10V, VDDQ= +2.6V +0.10V • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data st...

K4H56038D Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
K4H56038D
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• 200MHz Clock, 400Mbps data rate.
• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK )
• DLL aligns  DQ and DQS transition with CK transition
• MRS cycle with address key programs
  -. Read latency  3 (clock) for DDR400 , 2.5 (clock) for DDR333
  -. Burst length (2, 4, 8)
  -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package




Pinout

Connection Diagram


Specifications

Parameter Symbol Value Unit
Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1.5 W
Short circuit current IOS 50 mA



Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Sensors, Transducers
GP2Y0D340K
PAN3509DH-TXWA
Programmers, Development Systems
ARDUINO IIC/I2C 液晶模块
JTAG-SMT2
Motors, Solenoids, Driver Boards/Modules
IHSS57-36-20
ASD-B2-1521-B
Switches
US32DMRJ
HBGQ22P-11ET
Batteries, Chargers, Holders
ICR18650-28A
ICR18650-26F/h
Static Control, ESD, Clean Room Products
DPA5
PA800-A41
View more