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K4H510638E-TC

Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs -. ...

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K4H510638E-TC: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe DQS• Four banks operation• Differential clock inputs(CK and CK)•...

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Part Number:
K4H510638E-TC
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe DQS
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
   -. Read latency 2, 2.5 (clock)
   -. Burst length (2, 4, 8)
   -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package


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