Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition• MRS cycle with address key programs-. ...
K4H280438F-LB0: Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)̶...
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Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirec...
Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirec...
Features: • Double-data-rate architecture; two data transfers per clock cycle• Bidirec...
Parameter |
Symbol |
Value |
Unit |
Voltage on any pin relative to VSS |
VIN,VOUT |
-0.5 ~ 3.6 |
V |
Voltage on VDD & VDDQ supply relative to VSS |
VDD,VDDQ |
-1.0 ~ 3.6 |
V |
Storage temperature |
TSTG |
-55 ~ +150 |
°C |
Power dissipation |
PD |
1.5 |
W |
Short circuit current |
IOS |
50 |
mA |