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K4C89183AF

Features: • Fully Synchronous Operation- Double Data Rate (DDR)- Data input/output are synchronized with both edges of DS / QS.- Differential Clock (CLK and CLK) inputs- CS, FN and all address input signals are sampled on the positive edge of CLK.- Output data (DQs and QS) is aligned to the ...

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SeekIC No. : 004382678 Detail

K4C89183AF: Features: • Fully Synchronous Operation- Double Data Rate (DDR)- Data input/output are synchronized with both edges of DS / QS.- Differential Clock (CLK and CLK) inputs- CS, FN and all address...

K4C89183AF Data Sheet

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Part Number:
K4C89183AF
Supply Ability:
5000

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Product Details

Description



Features:

• Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
• Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Uni-directional Data Strobe
• Distributed Auto-Refresh cycle in 3.9us
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 4
• Organization : 4,194,304 words x 4 banks x 18 bits
• Power Supply Voltage VDD : 2.5V ± 0.125V
• VDDQ : 1.4V ∼ 1.9V
• 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
• Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
• Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD


Pinout

Connection Diagram


Specifications

Symbol Parameter Rating Units Notes
Vdd Power Supply Voltage -0.3 to 3.3 V  
VddQ Power Supply Voltage (for I/O buffer) -0.3 ~ VDD + 0.3 V  
VIN Input Voltage -0.3 ~ VDD + 0.3 V  
VOUT DQ pin Voltage -0.3 ~ VDDQ + 0.3 V  
VREF Input Reference Voltage -0.3 ~ VDDQ + 0.3 V  
TOPR Operating Temperature 0 to 85  Case Temp.
TSTG Storage Temperature -55 to 150  
TSOLDER Soldering Temperature(10s) 260  
PD Power Dissipation 2 W  
IOUT Short Circuit Output Current ± 50 mA  

Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.




Description

K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is  rganized as 4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge  hereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can operate fast core cycle compared with regular DDR SDRAM. K4C89183AF is suitable for Server, Network and other applications where large memory density and low power  onsumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading  ondition.




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