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IW4518B

Features: • Operating Voltage Range: 3.0 to 18 V• Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C• Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V sup...

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SeekIC No. : 004381471 Detail

IW4518B: Features: • Operating Voltage Range: 3.0 to 18 V• Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C• Noise margin (over full p...

IW4518B Data Sheet

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Part Number:
IW4518B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/13

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Product Details

Description



Features:

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
  1.0 V min @ 5.0 V supply
  2.0 V min @ 10.0 V supply
  2.5 V min @ 15.0 V supply


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP, SOIC
Package		 750
500		 mW
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
  +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
               SOIC Package: : - 7 mW/°C from 65° to 125°C


Description

The IW4518B Dual BCD Up-Counter consists two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.

The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.




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