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IW4043B

Features: • Operating Voltage Range: 3.0 to 18 V• Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25°C• Noise margin (over full package temperature range):1.0 V min @ 5.0 V supply2.0 V min @ 10.0 V supply2.5 V min @ 15.0 V supplyPinout...

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SeekIC No. : 004381429 Detail

IW4043B: Features: • Operating Voltage Range: 3.0 to 18 V• Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25°C• Noise margin (over full package...

IW4043B Data Sheet

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Part Number:
IW4043B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 A at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
Ptot Power Dissipation per Output Transistor 100 mW
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+		 750
500		 mW
Tstg Storage Temperature -65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mWfrom 65° to 125
SOIC Package: : - 7 mW/°C from 65° to 125


Description

The IW4043B types are quad cross-coupled 3-state CMOS NOR latces. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.




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