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IW4027B

Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supplyPinoutSpecifications ...

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SeekIC No. : 004381414 Detail

IW4027B: Features: · Operating Voltage Range: 3.0 to 18 V· Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C· Noise margin (over full package temperature range...

IW4027B Data Sheet

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Part Number:
IW4027B
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·  Operating Voltage Range: 3.0 to 18 V
·  Maximum input current of 1 mA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C
·  Noise margin (over full package temperature range):
    1.0 V min @ 5.0 V supply
    2.0 V min @ 10.0 V supply
    2.5 V min @ 15.0 V supply


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP, SOIC
Package		 500** mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)		 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
**Derating: - Plastic DIP from -55 to +100°C
- SOIC Package from -55 to +65°C
- Plastic DIP: - 10 mW/°C from +100 to +125°C
- SOIC Package: : - 7 mW/°C from +65 to +125°C


Description

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance.




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