IT8687R

IT8687R integrates six (6) line drivers, ten (10) line receivers, one ISA signal encoder, one (1) UART signal-mixing control logic, and one 24/48 MHz clock generator. The ISA signals; (1) SA12, SA13, SA14, SA15, DACK0#, DACK1#, DACK2#, DACK3#, AEN, RESET are encoded into three (3) signals -- RAD0, RAD1, RAD2. 16 UART interface signals are encoded into UIF0, UIF1, UIF2, UIF3, UIF4 to minimize the pin count and the package cost. This low power consumption chip is designed to serve as an interface between data terminal  equipment and data communication equipment in conformance with the EIA standard RS-232 specifications.