ISL88550A

Features: • Pb-Free Plus Anneal Available (RoHS Compliant)Application• DDR, DDR II, and DDR III Memory Power Supplies• Desktop Computers• Notebooks and Desknotes• Graphics Cards• Game Consoles• Networking and RAIDPinoutSpecificationsVIN to GND . . . . . . ...

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ISL88550A Picture
SeekIC No. : 004380648 Detail

ISL88550A: Features: • Pb-Free Plus Anneal Available (RoHS Compliant)Application• DDR, DDR II, and DDR III Memory Power Supplies• Desktop Computers• Notebooks and Desknotes• Graph...

floor Price/Ceiling Price

Part Number:
ISL88550A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Pb-Free Plus Anneal Available (RoHS Compliant)




Application

• DDR, DDR II, and DDR III Memory Power Supplies
• Desktop Computers
• Notebooks and Desknotes
• Graphics Cards
• Game Consoles
• Networking and RAID





Pinout

  Connection Diagram




Specifications

VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +25V
VDD, AVDD, VTTI to GND. . . . . . . . . . . . . . . . . . . . . .... . . -0.3V to 6V
SHDNA#, REFIN to GND. . . . . . . . . . . . . . . . . . . . ... . . . . -0.3V to 6V
SS, POK1, POK2, SKIP#, ILIM, FB to GND . . . . ..... . . . . . -0.3V to 6V
STBY#, TON, REF, UVP/OVP to GND. . . . . . ...... .-0.3V to AVDD+0.3V
OUT, VTTR to GND . . . . . . . . . . . . . . . . . . ... . . .-0.3V to AVDD+0.3V
LGATE to PGND1 . . . . . . . . . . . . . . . . . . .. . . . . . -0.3V to VDD+0.3V
UGATE to PHASE . . . . . . . . . . . . . . . . . . ..... . -0.3V to VBOOT +0.3V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
PHASE to PGND . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . -2V to +33V
VTT to GND. . . . . . . . . . . . . . . . . . . . . ... . . . . . . -0.3V to VTTI+0.3V
VTTS to GND. . . . . . . . . . . . . . . . . . . . .. . . . . . .-0.3V to AVDD+0.3V
PGND1, PGND2 to GND . . . . . . . . . . . . .. . . . . . . . . . . -0.3 to +0.3V
REF Short Circuit to GND.. . . . . . . . . . . . . . . . . . . . . . . .Continuous





Description

ISL88550A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two external N-Channel MOSFETs to generate output voltages down to 0.7V from a 2V to 25V input with output currents up to 15A. The LDO can source up to 2.5A and sink up to -2.0A continuously. Both the LDO output and the 10mA reference buffer output can be made to track the REFIN voltage via a built-in resistive divider. These features make the ISL88550A ideally suited for DDR memory applications in desktops, notebooks and graphics cards. The PWM controller in the ISL88550A uses constant-on-time PWM architecture with a programmable switching frequency of up to 600kHz. This control scheme handles wide input/output voltage ratios with ease and provides 100ns instant-on response to load transients while maintaining high efficiency and a relatively constant switching frequency. The ISL88550A offers full programmable UVP/OVP and skip mode options ideal in portable applications. Skip mode allows for improved efficiency at lighter loads. The VTT and VTTR outputs track to VREFIN/2. The high bandwidth of this LDO regulator allows excellent transient response without the need for bulk capacitors, thus reducing the cost and size. The buck controller and LDO regulators are provided with independent current limits. Adjustable loss-less fold-back current limit for the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low side synchronous MOSFET. Once overcurrent is removed, the regulator is allowed to enter soft-start again. This helps minimize power dissipation during short-circuit condition. Additionally, overvoltage and undervoltage protection mechanisms are built in. The ISL88550A allow flexible sequencing and standby power management using SHDNA#, and STBY# inputs.




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