ISL6614

Features:

• Provides four ACPI-Controlled Voltages
-5VDUAL USB/Keyboard/Mouse
-3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
-1.2VVID Processor VID Circuitry
-1.5VSB ICH4 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% over temperature (as applicable)
• Small Size; Very Low External Component Count
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• QFN Package:
- Near Chip Scale Package Footprint; Improved PCB
Efficiency; Thinner profile
• Pb-Free Available (RoHS Compliant)




Application

• ACPI-Compliant Power Regulation for Motherboards
- ISL6504: 5VDUAL is shut down in S4/S5 sleep states
- ISL6504A: 5VDUAL stays on in S4/S5 sleep states




Pinout






Specifications

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . .. . . . . . VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . .VPHASE - 0.3VDC to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
LGATE . . . . . . . .. . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 15VDC
GND - 8V (<400ns, 20µJ) to 30V (<200ns, VBOOT-GND<36V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . .. . . . .Class I JEDEC STD




Description

The ISL6504 and ISL6504A complement other power building blocks (voltage regulators) in ACPI-compliant designs for microprocessor and comp -uter applications. The IC integrates three linear controllers/regulators, switching, monitoring and control functions into a 16-pin wide-body SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5.

One linear controller generates the 3.3VDUAL/3.3VSB voltage plane from the ATX supply's 5VSB output, powering the south bridge and the PCI slots through an external NPN pass transistor during sleep states (S3, S4/S5). In active state (during S0 and S1/S2), the 3.3VDUAL/3.3VSB linear regulator uses an external N-channel pass MOSFET to connect the outputs directly to the 3.3V input supplied by an ATX power supply, for minimal losses.

A controller powers up the 5VDUAL plane by switching in the ATX 5V output through an NMOS transistor in active states, or by switching in the ATX 5VSB through a PMOS (or PNP) transistor in S3 sleep state. In S4/S5 sleep states, the ISL6504 5VDUAL output is shut down. In the ISL6504A, the 5VDUAL output stays on during S4/S5 sleep states. This is the only difference between the two parts; see Table 1.

An internal linear regulator supplies the 1.2V for the voltage identification circuitry (VID) only during active states (S0 and S1/S2), and uses the 3V3 pin as input source for its internal pass element. Another internal regulator outputs a 1.5VSB chip-set standby supply, which uses the 3V3DL pin as input source for its internal pass element. The 3.3VDUAL/3.3VSB and 1.5VSB outputs are active for as long as the ATX 5VSB voltage is applied to the chip.