ISL6559

Features:

* Multi-Phase Power Conversion
- 2, 3 or 4 Phase Operation
* Active Channel Current Balancing
* Precision rDS(ON) Current Sharing
- Lossless
-Low Cost
* Input Voltage: 12V or 5V Bias
* Precision CORE Voltage Regulation
-±1% System Accuracy Over Temperature
- Differential Remote Output Voltage Sensing
- Programmable Reference Offset
* Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 0.800V to 1.550V in 25mV Steps
- Dynamic VID Technology
* Programmable Droop Voltage
* Fast Transient Recovery Time
* Over Current Protection
* Digital Soft Start
* Threshold Sensitive Enable Input
* High Ripple Frequency (160kHz to 4MHz)
* QFN Package:
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile
* Pb-Free Available (RoHS Compliant)




Application

* AMD Hammer Family Processor Voltage Regulator
* Low Output Voltage, High Current DC-DC Converters
* Voltage Regulator Modules




Pinout






Specifications

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage. . . . . . . . . . .GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class TBD




Description

The ISL6559 provides core-voltage regulation by driving 2 to 4 interleaved synchronous-rectified buck-converter channels in parallel. Interleaving the channel timing results in increased ripple frequency which reduces input and output ripple currents. The reduction in ripple results in lower component cost, reduced dissipation, and a smaller implementation area.

The ISL6559 uses cost and space-saving rDS(ON) sensing for channel current balance, active voltage positioning, and over-current protection. Output voltage is monitored by an internal differential remote sense amplifier. A high-bandwidth error amplifier drives the output voltage to match the programmed 5-bit DAC reference voltage. The resulting compensation signal guides the creation of pulse width modulated (PWM) signals to control companion Intersil MOSFET drivers. The OFS pin allows direct offset of the DAC voltage from 0V to 50mV using a single external resistor. The entire system is trimmed to ensure a system accuracy of ±1% over temperature.

Outstanding features of this controller IC include Dynamic VID^TM technology allowing seamless on-the-fly VID changing without the need of any external components. Output voltage "droop" or active voltage positioning is optional. When employed, it allows the reduction in size and cost of the output capacitors required to support load transients. A threshold-sensitive enable input allows the use of an external resistor divider for start-up coordination with Intersil MOSFET drivers or any other devices powered from a separate supply.