ISL6537A

Features:

•Generates 5 Regulated Voltages
-Synchronous Buck PWM Controller for DDR V_DDQ
-3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR V_TT
-PWM Regulator for GMCH Core
-LDO Regulator for CPU/GMCH V_TT Termination
-LDO Regulator for DAC
•ACPI compliant sleep state control
•Glitch-free Transitions During State Changes
•Integrated V_REFBuffer
•V_DDQPWM Controller Drives Low Cost N-Channel MOSFETs
•250kHz Constant Frequency Operation
-Both PWM controllers are Phase Shifted 180°
•Tight Output Voltage Regulation
-All Outputs: ±2% Over Temperature
•Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
•Simple Single-Loop Voltage-Mode PWM Control Design
•Fast PWM Converter Transient Response
•Under and Overvoltage Monitoring
•OCP on the V_DDQSwitching Regulator
•Integrated Thermal Shutdown Protection
•Pb-Free Available (RoHS Compliant)




Application

•Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs
•Graphics cards - GPU and memory supplies
•ASIC power supplies
•Embedded processor and I/O supplies
•DSP supplies




Pinout






Specifications

5VSBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V
Absolute Boot Voltage, V_BOOT. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V_BOOT- V_PHASE. . . . . . . . . ... . +6.0V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD




Description

The ISL6537A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2 reference is provided as VREF. A second PWM controller, which requires external MOSFET drivers, is available for regulation of the GMCH Core voltage. An LDO controller is also integrated for the CPU VTT termination voltage regulation and the DAC. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter ISL6537A uses voltagemode control with fast transient response. The switching regulator ISL6537A provides a maximum static regulation tolerance of 2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTT termination voltage is within spec and operational. All outputs, except VDAC, have undervoltage protection. The switching regulator ISL6537A also has overvoltage and overcurrent protection. Thermal shutdown is integrated.