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ISL5640

Features: Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS 7.4 Bits at fIN = 1MHz Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW Wide Full Power Input Bandwidth. . . . . . . . . ...

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SeekIC No. : 004380004 Detail

ISL5640: Features: Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS 7.4 Bits at fIN = 1MHz Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW Power Down Mode . . . ....

ISL5640 Data Sheet

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Part Number:
ISL5640
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/14

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Product Details

Description



Features:

Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS
7.4 Bits at fIN = 1MHz
Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW
Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
SFDR at fIN = 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . .55dB
Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
On-Chip Sample and Hold Amplifiers
Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.0V
Offset Binary or Two's Complement Output Format
Dual 8-Bit A/D Converters on a Monolithic Chip
Pin Compatible Upgrade to AD9288


Application

Wireless Local Loop
PSK and QAM I&Q Demodulators
Medical Imaging
High Speed Data Acquisition


Pinout

Connection Diagram


Specifications

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC 


Description

The ISL5640 is a monolithic, dual 8-bit analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The ISL5640 features a 9-stage pipeline architecture. The fully pipelined architecture and an innovative input stage enable the ISL5640 to accept a variety of input configurations, singleended or fully differential. Only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. This allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation.

The ISL5640 has excellent dynamic performance while consuming less than 100mW power at 40MSPS. The A/D only requires a single +3.0V power supply. Data output latches are provided which present valid data to the output bus with a latency of 5 clock cycles.

The ISL5640 is offered in 20MSPS, 30MSPS, 40MSPS and 60MSPS sampling rates. 




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