ISL5314

Features: • 125MSPS output sample rate with 5V digital supply• 100MSPS output sample rate with 3.3V digital supply• 14-bit digital-to-analog (DAC) with internal reference• Parallel control interface for fast tuning (50MSPS control register write rate) and serial control int...

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ISL5314 Picture
SeekIC No. : 004379849 Detail

ISL5314: Features: • 125MSPS output sample rate with 5V digital supply• 100MSPS output sample rate with 3.3V digital supply• 14-bit digital-to-analog (DAC) with internal reference• Pa...

floor Price/Ceiling Price

Part Number:
ISL5314
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

• 125MSPS output sample rate with 5V digital supply
• 100MSPS output sample rate with 3.3V digital supply
• 14-bit digital-to-analog (DAC) with internal reference
• Parallel control interface for fast tuning (50MSPS control register write rate) and serial control interface
• 48-bit programmable frequency control
• Offset frequency register and enable pin for fast FSK
• Small 48-pin LQFP packaging





Application

• Programmable local oscillator
• FSK, PSK modulation
• Direct digital synthesis
• Clock generation





Pinout

  Connection Diagram




Specifications

Digital Supply Voltage DVDD to DGND . . . . . . . . .. . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to AGND . . . . . . . .. . . . . . . . . . . +5.5V
Grounds, AGND To DGND . . . . . . . . . . . . . . ... . . . . . -0.3V To +0.3V
Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . .. . . . . . . . . . . . 24mA





Description

The 14-bit ISL5314 provides acomplete Direct Digital Synthesizer (DDS) system in a single 48-pin LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital to analog converter) are integrated into a stand alone DDS.

The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. A 40-bit frequency tuning word can also be loaded via an asynchronous serial interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0, 90, 180 and 270 degrees, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator.

The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (WE). The processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting theUPDATE pin.






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