ISL35822

Features:

• 8 Lanes of Clock & Data Recovery and Retiming; 4 in Each Direction
• Differential Input/Output
• Wide Operating Data Rate Range: 2.488Gbps to 3.1875Gbps, and 1.244Gbps to 1.59325Gbps
• Ultra Low-Power Operation (163mW typical per lane, 1300mW typical total consumption, LX4 mode)
• Low Power Version Available for LX4 Applications
• 17mm Square Low Profile 192 pin 1.0mm Pitch EBGA-B Package
• Compliant to the IEEE 802.3 10GBASE-LX4(WWDM), 10GBASE-CX4, and XAUI Specifications
• Reset Jitter Domain
• Meets 802.3ae and 802.3ak Jitter Requirements with Significant Margin
• Received Data Aligned to Local Reference Clock for Retransmission
• Increase Driving Distance
• LX4: Up to 40 inches of FR-4 Traces or 500 Meters of MMF Fiber at 3.1875Gbps
• CX4: Over 15 meters of Compatible Cable
• Deskewing and Lane-to-Lane Alignment
• 0.13mm Pure-Digital CMOS Technology
• 1.5V Core Supply, Control I/O 2.5V Tolerant
• Clock Compensation
• Tx/Rx Rate Matching via IDLE Insertion/Deletion up to ±100ppm Clock Difference
• Receive Signal Detect and 16 Levels of Receiver Equalization for Media Compensation
• CML CX4 Transmission Output with 16 Settable Levels of Pre-Emphasis, Eight on XAUI Side
• Single-Ended or Differential Input Lower-Speed Reference Clock
• Ease of Testing
• Complete Suite of Ingress-Egress Loopbacks
• Full 802.3ae Pattern Generation and Test, including CJPAT & CRPAT
• PRBS (both 2²³-1 and 13458 byte) Built-In Self Tests, Error Flags and Count Output
• JTAG and AC-JTAG Boundary Scan
• Long Run Length (512 bit) Frequency Lock Ideal for Proprietary Encoding Schemes
• Extensive Configuration and Status Reporting via 802.3 Clause 45 Compliant MDC/MDIO Serial Interface
• Automatic Load of ISL35822 Control and all XENPAK Registers from EEPROM or DOM Circuit




Specifications

SYMBOL	PARAMETER	MIN	MAX	UNITS
VDDPR	2.5V Protection Power Supply Voltage	-0.5, VDD - 0.5	2.6, VDD + 2.0	V
VDDA, VDD, VDDAC, VDDAV	All Other Power Supply Voltages	-0.5	1.65	V
VINCML	CML DC Input Voltage	-0.5	VDD + 0.5	V
IOUTCML	CML Output Current	- 50	+50	mA
VINCMS1	1.2V CMOS Input Voltage	-0.5	VDD + 0.5	V
VINCMS2	1.5V CMOS Input Voltage	-0.5	VDD + 0.5	V
VINCMS3	2.5V Tolerant CMOS Input Voltage	-0.5	2.6	V
Tstg	Storage Temperature	- 55	125	°C
Tj	Junction Temperature	- 55	125	°C
TSOL	Soldering Temperature (10s)		220	°C
VESD	Maximum Input ESD (HBM)	-2000	2000	V

Description

The ISL35822 is a fully integrated octal 2.488Gbps to 3.1875Gbps Clock and Data Recovery (CDR) circuit and Retimer ideal for high bandwidth serial electrical or optical communications systems. It extracts timing information and data from serial inputs at 2.488Gbps to 3.1875Gbps, covering 10 Gigabit Fiber Channel (10GFC) and IEEE 802.3 specified 10 Gigabit Ethernet eXtended Attachment Unit Interface (XAUI) rates. Each ISL35822 accepts two sets of four high-speed differential serial signals, re-times them with a local Reference Clock, reduces jitter, and delivers eight clean high-speed signals. The ISL35822 provides a full-function XAUI-to-10GBASE-CX4 PMA/PMD (compatible with the IEEE 802.3ak specification), and also can be configured to provide the electrical portion of a XAUI-to-10GBASE-LX4 PMA/PMD, needing only laser drivers and photo detectors to be added. In both these applications, the XAUI side can be configured to implement the XENPAK MSA_R3.0 specification, including full NVR and DOM support. The XPAK and X2 specifications currently all reference the XENPAK specification, and are supported in exactly the same manner. The ISL35822 can also be used to enhance a single full-duplex 10 Gigabit XAUI link, extending the driving distance of the high-speed (2.488Gbps to 3.1875Gbps) differential traces to 40 inches of FR4 PCB (assuming a proper impedance-controlled layout).