ISL22349

Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to +150
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V_CC+0.3
V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V_CC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . .. . . . .+300
I_W (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup (Note 4) . . . . . . . . . . . . . . . . . Class II, Level B @ +125
ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV
(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

NOTES:
3. _JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins.

The ISL22349 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit.

The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I²C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power up the device recalls the contents of the two DCP's IVR to the corresponding WRs.

The DCPs can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing.