Features: · 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide.· 3.3 V optimized transistor with 5 V I/O interface · 2 - input NAND delay of 0.210 ns (typ) with fanout = 2.· Broad I/O func...
ISB35000: Features: · 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide.· 3.3 V optimized transis...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
SupplyVoltage,Vdd | -0.5 V to +6.0 V |
Input or Output Voltage | -0.5 V to (Vdd + 0.5V) |
DC Forward Bias Current, Input or Output | -24mA source, +24mA sink |
Storage Temperature Ceramic | -65 to 150 degrees Centigrade |
Storage Temperature Plastic | -40 to 125 degrees Centigrade |
The ISB35000 array series uses a high performance, low voltage, triple level metal, HCMOS 0.5 micron process to achieve sub-nanosecond internal speeds while offering very low power dissipation and high noise immunity. The potential total gate count ranges above 1 million equivalent usable gates. The array operates over a Vdd voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over 600 signals and 1000 pins dependent upon the package technology utilized. A Sea of I/O approach has been followed to give a solution to today's problems of drive levels and specialized interface standards. The array does not utilize a set bond pad spacing but allows for pad spacings from 80 microns upwards.
The I/O can be configured for circuits ranging from low voltage CMOS and TTL to 200 mHz plus low swing differential circuits. Standards like GTL, SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0 Volt interfaces are currently being addressed. A specialized set of impedance matched transmission line driver LVTTL type circuits are also available with 25, 35, 45, and 55 Ohm output impedance. These buffers sacrifice direct current capabilities for matching positive and negative voltage and current waveforms.