Features: • High-speed access time: 20, 45 ns• Automatic power-down when chip is deselected• CMOS low power operation- 17 W (typical) CMOS standby- 50 mW (typical) operating• TTL compatible interface levels• Single 3.3V power supply• Fully static operation: no c...
IS65LV256AL: Features: • High-speed access time: 20, 45 ns• Automatic power-down when chip is deselected• CMOS low power operation- 17 W (typical) CMOS standby- 50 mW (typical) operating•...
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Features: • High-speed access time: 35, 45 ns• Low active power: 100 mW (typical)̶...
Symbol | Parameter | Value | Unit |
VTERM | Terminal Voltage with Respect to GND | 0.5 to +4.6 | V |
TBIAS | Temperature Under Bias | 55 to +125 | |
TSTG | Storage Temperature | 65 to +150 | |
PT | Power Dissipation | 0.5 | W |
IOUT | DC Output Current (LOW) | 20 | mA |
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The ISSI IS62/65LV256AL is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum.
WhenCE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IS62/65LV256AL is available in the JEDEC standard 28-pin SOJ, 28-pin SOP, and the 28-pin 450-mil TSOP package.