Features: • Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium™ or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin LQFP and 119-pin PBGA package
• Single +3.3V, +10%, 5% power supply
• Power-down snooze modePinout
Specifications
| Symbol |
Parameter |
Value |
Unit |
| TBIAS |
Temperature Under Bias |
40 to +85 |
°C |
| TSTG |
Storage Temperature |
55 to +150 |
°C |
| PD |
Power Dissipation |
1.6 |
W |
| IOUT |
Output Current (per I/O) |
100 |
mA |
| VIN, VOUT |
Voltage Relative to GND for I/O Pins |
0.5 to VCCQ + 0.3 |
V |
| VIN |
Voltage Relative to GND for
for Address and Control Inputs |
0.5 to VCC + 0.5 |
V |
| VCC |
Voltage on Vcc Supply Relatiive to GND |
0.5 to 4.6 |
V |
`Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
`This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
`This device contains circuitry that will ensure the output devices are in High-Z at power up.
DescriptionThe ICSI IS61SP12832 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. IS61SP12832 is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The IS61SP12832 integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP12832 and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
IS61SP12832 Data Sheet
