Features: • 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
• Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
• Industrial temperature available
• Lead-free availablePinout
Specifications
|
Symbol |
Parameter |
Value |
Unit |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
PD |
Power Dissipation |
1.6 |
W |
|
IOUT |
Output Current (per I/O) |
100 |
mA |
|
VIN, VOUT |
Voltage Relative to VSS for I/O Pins |
0.5 to VDDQ + 0.3 |
V |
|
VIN |
Voltage Relative to VSS for
for Address and Control Inputs |
0.3 to 4.6 |
V |
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DescriptionThe 4 Meg 'NLP/NVP' product family IS61NVP25618A feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles IS61NVP25618A are eliminated when the bus switches from read to write, or write to read. This IS61NVP25618A integrates a 2-bit burst counter , high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers IS61NVP25618A are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW.
Write cycles IS61NVP25618A are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected
IS61NVP25618A Data Sheet
