IS61LV6464

Features:

* Fast access time:
    -100 MHz; 6 ns-83 MHz
* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Pentium(TM) or linear burst sequence control using MODE input
* Five chip enables for simple depth expansion and address pipelining
* Common data inputs and data outputs
* Power-down control by ZZ input
* JEDEC 128-Pin TQFP 14mm x 20mm package
* Single +3.3V power supply
* 2.5V VDDQ (I/O supply)
* Control pins mode upon power-up:
    MODE in interleave burst mode
    ZZ in normal operation mode
  These control pins can be connected to GNDQ or VDDQ to alter their power-up state


Pinout




Specifications

Symbol	Parameter	Value	Unit
PD	Power Dissipation	1.0	W
IOUT	Output Current (per I/O)	100	mA
VIN, VOUT	Voltage Relative to GND for I/O Pins	0.5 to VDDQ + 0.3	V
VIN	Voltage Relative to GND for for Address and Control Inputs	0.5 to 5.5	V
VDD	Voltage on VDD Supply Relative to GND	0.5 to 4.6	V

Description

The ISSI IS61LV6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium(TM), 680X0(TM), and PowerPC(TM) microprocessors.  It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.